1. Field
Exemplary embodiments of the present invention relate to a clock generation circuit.
2. Description of the Related Art
As the operation speed of an integrated circuit increases, clocking power consumption and speed bottlenecking become serious issues. In order to solve such problems, the integrated circuit operates at low clock speed and only the I/O circuit operates at high speed. Additionally, the integrated circuit uses multiple internal clocks having multiple phases.
For example, four internal clocks, each of which has a phase difference of 90°, are generated from an external clock. Conducting internal operations using four internal clocks that operate at low-speed alleviates the internal operation speed problems, while the I/O operation speed is still high. The I/O operations are conducted by serialization of the four internal clocks at the input and output of the internal circuit.
The internal clocks having multiple phases can be made by generating two internal clocks having phases of 0° and 90° and generating two internal clocks having phases of 180° and 270°, which are inverted versions of the two former internal clocks. That is, a pair of the internal clocks having phases of 0° and 180° are generated, and the other pair of the internal clocks having phases of 90° and 270° are generated. The phase relationship between the internal clocks should be always maintained.
FIG. 1 is a diagram illustrating a clock generation circuit for generating internal clocks CK1 to CK4 having four difference phases. In FIG. 1, each phase difference among the internal clocks CK1 to CK4 is 90°.
Referring to FIG. 1, the clock generation circuit may include D flip-flops DFF1 and DFF2 and inverters I1 and I2.
The first D flip-flop DFF1 may output a value of an input node D to an output node Q at the rising edge of a reference clock CK. When a reset signal RSTB is enabled, the first D flip-flop DFF1 may low-disable the signal of the output node Q. The output signal of the first D flip-flop DFF1 may be inverted by the inverter I1 and input to the input node D of the first D flip-flop DFF1. In this case, a clock output from the output node Q of the first D flip-flop DFF1 may be the first clock CK1 having a phase of 0°, and a clock input to the input node D of the first D flip-flop DFF1 may be the third clock CK3 having a phase of 180°.
The second D flip-flop DFF2 may output a value of an input node D to an output node Q at the rising edge of a reference inversion clock CKB. The reference inversion clock CKB may have the opposite phase to the clock CK. When the reference reset signal RSTB is enabled, the second D flip-flop DFF2 may low-disable the signal of the output node Q. The signal output to the output node Q of the second D flip-flop DFF2 may be inverted by the inverter I2 and input to the input node D of the second D flip-flop DFF2. In this case, a clock output from the output node Q of the second D flip-flop DFF2 may be the second clock CK2 having a phase of 90°, and a clock input to the input node D may be the fourth clock CK4 having a phase of 270°.
In order for the integrated circuit to operate, the first to fourth clocks CK1 to CK4 generated by the clock generation circuit of FIG. 1 need to have a constant phase relationship.
FIG. 2 is a diagram illustrating problems which may occur in the clock generation circuit of FIG. 1.
As illustrated in FIG. 2, it is assumed that at time point A the duty ratios of the reference clock CK and the reference inversion clock CKB are distorted due to noise generated in the integrated circuit. The distortion makes the first clock CK1 fail to toggle at time point T1, when it is supposed to. However, the second clock CK2 has shifted properly at time point T2, and thus the first to fourth clocks CK1 to CK4 have mismatched phase relationships as illustrated in FIG. 2. That is, the first to fourth clocks CK1 to CK4 have phases of 90°, 270°, 0°, and 180°. With the Internal clocks CK1 to CK4 having mismatched phase relationships, the integrated circuit cannot operate properly.